It is known to make bipolar analog circuits that are capable of sustaining a voltage of about 40 volts. Such prior art circuits have a drawback in that they are slow to switch and consume a large amount of area per transistor.
Prior art complementary bipolar technologies in bulk silicon use one of the following processes in order to isolate transistors: PN junction isolation; LOCOS (Local Oxidation of Silicon) isolation; or trench isolation. Since all of these are in bulk material they are all subject to parasitic interaction with the substrate. One dielectrically isolated technology uses an anisotropic etch of a &lt;100&gt; silicon crystal. The etched surface is oxidized and deposited with a thick layer of polysilicon to form islands of single crystal silicon. After this process, the wafer is inverted, polished and etched back to expose the silicon islands in which the transistors are formed. Problems associated with this technology are grind and etch-back non-uniformity, limited wafer diameter, large device size, device size dependent on isolation depths, and high parasitic AC impedance with polysilicon substrates.